1. Field
The example embodiments relate to a semiconductor memory device, and more particularly to a semiconductor memory device including a write recovery time control circuit and a method of controlling a write recovery time of the semiconductor memory device.
2. Description
A synchronous semiconductor memory device may input and output data in synchronization with an external clock. Due to an increased operation speed of a Dynamic Random Access Memory (DRAM), a word line (WL) may be disabled by a pre-charge command before data is sufficiently written into a memory cell in response to a write command. A column selecting line (CSL) enable signal and a pre-charge command may be generated after a write command is generated, and the time period between the generation of the CSL enable signal. The generation of the pre-charge command may be referred to as a write recovery time (tWR).
A semiconductor memory device capable of controlling a write recovery time may help to ensure proper operation of a synchronous semiconductor memory device.